Liquid crystal display (“LCD”) devices are driven based on electro-optical characteristics of a liquid crystal material. The liquid crystal material has an intermediate state between a solid crystal and an isotropic liquid. The liquid crystal material is fluid like the isotropic liquid, and molecules of the liquid crystal material are regularly arranged like the solid crystal. An alignment direction of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. Light passes through the LCD device along the alignment direction of the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment direction of the liquid crystal molecules may be altered, and images may be displayed.
Active matrix liquid crystal display (“AMLCD”) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display fast moving images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one another. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. The direction of the electric field is perpendicular to the substrates. The LCD device has relatively high transmittance and a large aperture ratio.
However, the LCD device may have narrow viewing angles. To increase the viewing angles, various modes have been proposed. Among these modes, an in-plane switching (IPS) mode of the related art will be described with reference to accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to a first embodiment of the related art.
In FIG. 1, the IPS mode LCD device according to the first embodiment of the related art includes a lower substrate 10 and an upper substrate 40, and a liquid crystal layer LC is interposed between the lower substrate 10 and the upper substrate 40.
A thin film transistor T, common electrodes 30 and pixel electrodes 32 are formed at each pixel P on the lower substrate 10. The thin film transistor T includes a gate electrode 12, a semiconductor layer 16, and source and drain electrodes 20 and 22. The semiconductor layer 16 is disposed over the gate electrode 12 with a gate insulating layer 14 therebetween. The semiconductor layer 16 includes an active layer 16a and an ohmic contact layer 16b. The source and drain electrodes 20 and 22 are formed on the semiconductor layer 16 and are spaced apart from each other.
Although not shown in the figure, a gate line is formed along a first side of the pixel P, and a data line is formed along a second side of the pixel P perpendicular to the first side. A common line is further formed on the lower substrate 10. The common line provides the common electrodes 30 with voltage.
A black matrix 42 and a color filter layer 44 are formed on an inner surface of the upper substrate 40. The black matrix 42 is disposed over the gate line, the data line and the thin film transistor T. The color filter layer 44 is disposed at the pixel P.
Liquid crystal molecules of the liquid crystal layer LC are driven by a horizontal electric field 50 induced between the common electrodes 30 and the pixel electrodes 32.
The lower substrate 10, including the thin film transistor T, the common electrodes 30 and the pixel electrodes 32, may be referred to as an array substrate. The upper substrate 40, including the black matrix 42 and the color filter layer 44, may be referred to as a color filter substrate.
The array substrate may be manufactured through 5 mask processes. That is, the gate electrode and the gate line are formed through a first mask process. The semiconductor layer, including the active layer and the ohmic contact layer, is formed through a second mask process. The source and drain electrodes and the data line are formed through a third mask process. A passivation layer and a contact hole are formed through a fourth mask process. The common electrodes and the pixel electrodes are formed through a fifth mask process.
In the IPS mode LCD device, the common electrodes 30 and the pixel electrodes 32 are formed on the same substrate 10. A large amount of light from a light source (not shown) is blocked due to the electrodes 30 and 32. Accordingly, the IPS mode LCD device has relatively low brightness.
To increase the brightness, the common electrodes 30 and the pixel electrodes 32 have been formed of a transparent conductive material. Even though the electrodes are transparent, light is not transmitted entirely through the electrodes. That is, some areas of the electrodes under the electric field induced between the electrodes can be used for an aperture ratio. However, the brightness of the IPS mode LCD device is generally increased on the whole when the electrodes are formed of a transparent conductive material.
Meanwhile, the mask process includes many steps of coating a thin film with photoresist, exposing the photoresist to light, developing the photoresist, etching the thin film, and removing the photoresist. Therefore, 4 mask processes for the IPS mode LCD device have been proposed to decrease the manufacturing costs and time. By using a half tone or slit mask, the active layer and the source and drain electrodes are formed through the same mask process.
An IPS mode LCD device including an array substrate, which is manufactured through 4 mask processes in the related art, will be described hereinafter with reference to the attached drawing.
FIG. 2 is a cross-sectional view of an IPS mode LCD device including an array substrate according to a second embodiment of the related art.
In FIG. 2, the IPS mode LCD device includes a lower substrate 50 and an upper substrate 80, which are spaced apart from each other. The IPS mode LCD device further includes a liquid crystal layer LC interposed between the lower and upper substrates 50 and 80.
A thin film transistor T, pixel electrodes 70 and common electrodes 72 are formed at each pixel P on the lower substrate 50. The thin film transistor T includes a gate electrode 52, a semiconductor layer 56, and source and drain electrodes 62 and 64. The semiconductor layer 56 is disposed over the gate electrode 52 with a gate insulating layer 54 therebetween. The semiconductor layer 56 includes an active layer 56a and an ohmic contact layer 56b. The source and drain electrodes 62 and 64 are formed on the semiconductor layer 56 and are spaced apart from each other. The common electrodes 72 and the pixel electrodes 70 are formed of a transparent conductive material, for example, indium tin oxide (ITO).
Although not shown in the figure, a gate line (not shown) is formed along a first side of the pixel P, and a data line 66 is formed along a second side of the pixel P perpendicular to the first side. A common line (not shown) is further formed on the lower substrate 50. The common line provides the common electrodes 72 with voltage. Another semiconductor layer 58 is formed under the data line 66.
A black matrix 82 and a color filter layer 84 are formed on an inner surface of the upper substrate 80. The black matrix 82 is disposed over the gate line (not shown), the data line 66 and the thin film transistor T. The color filter layer 84 is disposed at the pixel P.
Here, the semiconductor layers 56 and 58 are partially exposed at sides of each of the source and drain electrodes 62 and 64 and the data line 66. When light from a light source is irradiated to the IPS mode LCD device including the above-mentioned structure, hydrogen atoms in the semiconductor layers 56 and 58 are excited due to the light, and currents may occur. The currents change according to a dimming frequency of the light source, and a coupling capacitance may be formed due to signal interference between the data line 66 and the common and pixel electrodes 72 and 70 adjacent to the data line 66. The coupling capacitance may cause a wavy noise in the displayed image.
More particularly, a backlight is disposed at a rear side of an LC panel of an LCD device. The backlight is driven depending on a dimming frequency to obtain a clear contrast between brightness and darkness. The backlight operates very fast according to low and high states of the frequency. According to this, light from the backlight is irradiated to the LC panel slightly differently, and the semiconductor layer acts like on and off modes. There is a potential difference between the adjacent data line and common electrode due to this characteristic of the active layer, and a wavy noise occurs on displayed images of the LC panel. The wavy noise decreases the quality of the LCD device. The wavy noise shows in the LCD device including an array substrate which is manufactured through 4 mask processes.